Verilog Week (with hands on labs):

One Week long crash cource with depth in Verilog design entry and verification with application project

• Day-1 : Verilog for Digital Design and test bench & test patterns - Automation Verification
• Day-2 : Logic Gates and & simulation with - DigNISim executor
• Day-3 : Combinatorial logic and encoder/decoders
• Day-4 : Sequential logic and registers, PISO and SIPO, LFSR
• Day-5 : Memory - RAM, ROM, Dual Port and Queues
• Day-6: State Machines and coding for control and digital communication
• Day-7: Timing issues and optimisation in coding + Project specification problem-statement

Bonus - Next 21 days of project with support on line.

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